Vertical memory structure with array interconnects and method for producing the same

ABSTRACT

Disclosed herein is a method and apparatus for fabricating a memory device. The memory device has a vertical stack of alternating layers of conductive and insulating layers wherein a top layer and a bottom layer are insulating layers. A plurality of vias is formed through the vertical stack from the top layer to the bottom layer. A memory layer disposed adjacent the conductive layers in the vias. A selector device disposed adjacent the memory layer wherein the selector device comprises multiple layers of dissimilar metal oxides. A lateral electrical contact to the memory layer through the conductive layer. And a top contact electrically connected to the conductive layer through a portion of the memory layer and the portion of the memory layer wherein the portion of the memory layer is configured to store data therein.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application claims is a divisional application of U.S. patentapplication Ser. No. 15/132,609, filed Apr. 19, 2016, which is hereinincorporated by reference.

BACKGROUND OF THE DISCLOSURE

Field of the Disclosure

Embodiments of the present disclosure generally relate to an electronicdevice, and more specifically, to a 3D memory cell.

Description of the Related Art

The heart of a computer is memory. The memory is typically used forstoring programs, routines, a computer state, or other bits ofinformation used in the operation and control of computers. Decreasingthe size of computers has necessitated the reduction in the spaceavailable for memory cells while the requirements for larger memorycapacity have continued to grow.

Phase change memory (PCM) is a type of non-volatile memory technology.PCM is an emerging technology and a candidate for storage class memory(SCM) applications and a serious contender to dislodge NOR and NANDflash memory in solid state storage applications and, in the case ofNAND flash, solid-state drives (SSDs). PCM functions based uponswitching a memory cell, typically based on chalcogenides such asGe₂Sb₂Te₅, between two stable states, a crystalline state and anamorphous state, by heating the memory cell. To heat the memory cell, anelectrical current flows through the PCM cell.

PCM cells are arranged in an array, and each PCM cell is coupled with aselecting switch such as an ovonic threshold switch (OTS). Word lines(WL) and bitlines (BL) are arranged so that each memory cell can beprogrammed or queried. A row of PCM cells is activated by a single wordline WL and each one of the PCM cells in that row will affect thebitline BL to which it is electrically connected according to the stateof the PCM cells, i.e. according to the PCM cells being in their high(amorphous) or low (crystalline) resistance state.

The incorporation of 3D elements is difficult from a wiring perspectivedue to complexity. Electrically isolating each memory element andaddressing adjacent devices that are not only separated in the lateraldirection have proven to be problematic. The high density devicespromote sneak currents between the elements that make reading the memoryelement difficult or inaccurate.

Therefore, there is a need for an improvement in the high density ofdevices in 3D memory.

SUMMARY OF THE DISCLOSURE

Disclosed herein is a method and apparatus for fabricating a memorydevice. In one embodiment, the memory device has a vertical stack ofalternating layers of conductive and insulating layers wherein a toplayer and a bottom layer are insulating layers. A plurality of vias isformed through the vertical stack from the top layer to the bottomlayer. A memory layer disposed adjacent the conductive layers in thevias. A selector device disposed adjacent the memory layer wherein theselector device comprises multiple layers of dissimilar metal oxides. Alateral electrical contact to the memory layer through the conductivelayer. And a top contact electrically connected to the conductive layerthrough a portion of the memory layer and the portion of the memorylayer wherein the portion of the memory layer is configured to storedata therein.

In a second embodiment, a memory device is disclosed in a verticalsubstrate stack having alternating layers of conductive layers andinsulating layers, wherein the vertical stack has one more insulatinglayer than conductive layers and a bottom layer being an etch stop layerand the top layer being one of the insulating layers. The memory devicehas a plurality of vias disposed through the vertical stack the toplayer to the etch stop layer. The memory device also has a metal oxidelayer adjacent the conductive layers in the vias configured to store avalue of resistance at discrete locations along the metal oxide layerand a plurality of layers disposed adjacent the memory layer. A topcontact is electrically connected to the conductive layer through theplurality of layers at one of the discrete locations along the metaloxide layer.

In yet a third embodiment, a method for fabricating a memory cellcomponent in a substrate is disclosed. In the method, an etch-stop layeris deposited on a substrate. Alternating layers of conductor andinsulator materials are deposited over said etch-stop layer to create avertical stack wherein the first and last layer is formed from theconductor material. A hardmask layer is then deposited on the verticalstack. A via having walls is etched through the vertical stack to exposethe etch-stop layer. A first layer is deposited on the wall of the via.A second layer is deposited on the first layer. A third layer isdeposited on the second layer. A fourth layer is deposited on the thirdlayer. A top conductor is deposited on the fourth layer for forming oneor more memory cells electrically connected to a portion of said topconductor and the layer of conducting material.

In yet a fourth embodiment, a memory device is disclosed in a verticalstack of alternating layers of conductive and insulating layers whereina top layer and a bottom layer are insulating layers. Pluralities ofvias are disposed through the vertical stack from the top layer to thebottom layer. A memory layer is disposed adjacent the conductive layersin the vias. A selector device is disposed adjacent the memory layer,wherein the selector device comprises multiple layers of dissimilarmetal oxides. The multiple layers of dissimilar metal oxides have afirst layer of TiO₂ of about 21 nm thick, a second layer of Al₂O₃ ofabout 2 nm thick, and a third layer of TiO₂ of about 21nm thick whereinthe thickness for each of the first layer and the third layer is greaterthan the thickness of the second layer. One or more lateral electricalcontacts to the memory layer is provided through the conductive layer. Atop contact electrically connects to the one or more lateral electricalcontacts through a portion of the memory layer and the portion of thememory layer is configured to store data therein.

BRIEF DESCRIPTION OF THE DRAWINGS

So that the manner in which the above recited features of the presentdisclosure can be understood in detail, a more particular description ofthe disclosure, briefly summarized above, may be had by reference toembodiments, some of which are illustrated in the appended drawings. Itis to be noted, however, that the appended drawings illustrate onlytypical embodiments of this disclosure and are therefore not to beconsidered limiting of its scope, for the disclosure may admit to otherequally effective embodiments.

FIG. 1 is a block diagram of an example processing system.

FIG. 2 illustrates a side plan view an example vertical stack ofalternating layers of conductive and insulator materials, in accordancewith certain embodiments of the present disclosure.

FIG. 3 illustrates a side plan view of two vias formed in the examplevertical stack of alternating layers of conductive and insulatormaterials, in accordance with certain embodiments of the presentdisclosure.

FIG. 4 illustrates a perspective view of the example vertical stacks ofFIG. 3, in accordance with certain embodiments of the presentdisclosure.

FIG. 5 illustrates a plan view of the example vertical stack in FIG. 3having material deposited for forming a memory cell, in accordance withcertain embodiments of the present disclosure.

FIG. 6 illustrates a plan view of the example vertical stack in FIG. 5having the devices formed therein, in accordance with certainembodiments of the present disclosure.

FIG. 7 illustrates a cross-sectional view through a conductive layer ofthe example vertical stack of FIG. 6, in accordance with certainembodiments of the present disclosure.

To facilitate understanding, identical reference numerals have beenused, where possible, to designate identical elements that are common tothe figures. It is contemplated that elements disclosed in oneembodiment may be beneficially utilized on other embodiments withoutspecific recitation.

DETAILED DESCRIPTION

In the following, reference is made to embodiments of the disclosure.However, it should be understood that the disclosure is not limited tospecific described embodiments. Instead, any combination of thefollowing features and elements, whether related to differentembodiments or not, is contemplated to implement and practice thedisclosure. Furthermore, although embodiments of the disclosure mayachieve advantages over other possible solutions and/or over the priorart, whether or not a particular advantage is achieved by a givenembodiment is not limiting of the disclosure. Thus, the followingaspects, features, embodiments and advantages are merely illustrativeand are not considered elements or limitations of the appended claimsexcept where explicitly recited in a claim(s). Likewise, reference to“the disclosure” shall not be construed as a generalization of anyinventive subject matter disclosed herein and shall not be considered tobe an element or limitation of the appended claims except whereexplicitly recited in a claim(s).

Disclosed is a method and apparatus for fabricating a memory cell. Anetch-stop layer is deposited on a substrate. Alternating layers ofconductor and insulator materials are deposited over said etch-stoplayer to create a vertical stack wherein the first and last layer isformed from the conductor material. A hardmask layer is deposited on thevertical stack. A via having walls is etched through the vertical stackto expose the etch-stop layer. A first layer is deposited on the wall ofthe via. A second layer is deposited on the first layer. A third layeris deposited on the second layer. A fourth layer is deposited on thethird layer. A top conductor is deposited on the fourth layer. Finally,one or more memory cells are formed in the via and electricallyconnected to a portion of said top conductor and the layer of conductingmaterial. The memory cell is configured to store data therein.

FIG. 1 is a block diagram of a processing system 100 having a processingdevice 102 and memory cell 104. The memory cell 104 comprises memorycells that are arranged in an array formation of rows and columns. Theprocessing device 102 interfaces with the array of memory cells via arow decoder 106 and column decoder 108. Individual memory cells arecontrolled by word lines that may extend along the rows of the array andbit lines that may extend along columns of the array. A memory cell mayexist at a junction between the word and bit lines. During a read/writecycle, a row decoder selects a row page of memory cells to be read fromor written to. Likewise, the column decoder selects a column address ofmemory cells for the read/write cycle. In certain embodiments of thepresent disclosure, each memory cell (e.g., at a junction between theword and bits lines) may include at least one of a memory material (e.g.a resistive RAM (RRAM) element such as a metal oxide, or a phase changememory (PCM) cell (e.g., using phase change material) or a selector legsuch as an ovonic threshold switch (OTS)).

FIG. 2 illustrates a side plan view an example vertical stack 210 ofalternating layers of a conductive layer 206 of material and aninsulator layer 204 of material, in accordance with certain embodimentsof the present disclosure. The vertical stack 210 may be disposed on topof an etch-stop layer 202 in a substrate. A hardmask layer 208 may beformed on top of the vertical stack 210. The vertical stack 210 may beformed on the etch-stop layer 202 with the first and last layer prior tothe hardmask layer 208 being the insulator material such as insulatorlayer 204. The conductive layer 206 is formed between two of theinsulator layer 204. Thus, the vertical stack 210 has at least oneadditional insulator layer 204 than conductive layers 206. For example,the vertical 210 may have 7 layers of alternating isolative andconductive material wherein 4 of the 7 layers are the insulator layers204 and 3 of the layers are the conductive layers 206. The verticalstack 210 may comprise any number of insulator and conductor layers 204,206, in an alternating fashion as illustrated.

The etch-stop layer 202 may be deposited over a substrate (not shown).The vertical stack 210 of conductor and insulator layers 206, 204 aredeposited on the etch-stop layer 202 in an alternating pattern. Incertain embodiments, the etch-stop layer 202 can be made of any materialthat does not etch in a fluorine containing plasma, such as chrome,magnetic metal, or an oxide that does not etch in fluorine such asaluminum oxide.

In certain embodiments, the insulator layer 204 is formed from anon-conductive material. That is, the insulator layer 204 is notelectrically conductive and impedes the flow of electrons therethrough.For example, the insulator layer 204 can be silicon dioxide (SiO₂) orother suitable electrically insulated material. A thickness 222 of theinsulator layers 204 may range from about 10 nanometers to about 100nanometers, such as about 10 nanometers.

The conductive layer 206 is electrically conductive. The conductivelayer 206 may be formed from a metal material. For example, theconductive layer may be metal compound comprising one or more oftitanium (Ti), tungsten (W), copper (Cu), molybdenum (Mo), chromium(Cr), gold (Au), tantalum (Ta), a polycrystalline form of silicon, orother suitably electrically conductive material. A thickness 224 of theconductor layers 206 may range from about 10 nanometers to about 100nanometers, such as about 10 nanometers. In certain embodiments, thethickness 224 of the conductive layer 206 may be substantially similarto the thickness 224 of the insulator layers 204. In certainembodiments, the thickness 222 of the conductive layer 206 may be lessthan the thickness 224 of the insulator layers 204.

The hardmask layer 208 is deposited over the vertical stack 210 and isused as an etch mask. The hardmask layer 208 facilitates etching of theunderlying vertical stack 210 and may be formed from one or more layersof materials. For example, the hardmask layer 208 may be formed from alayer of silicon oxide (SiO₂) and a layer of chrome (Cr). A layer of Crmay be deposited on a top surface 201 of the vertical stack 210. Asubsequent layer of SiO₂ may be deposited on the Cr to form the hardmasklayer 208. Alternately, the hardmask layer 208 may be formed from adiamond like carbon (DLC) material or a non-etchable oxide (e.g. Al₂O₃).

FIG. 3 illustrates a side plan view of two vias 310A, 310B formed in theexample vertical stack 210 of alternating layers of conductive andinsulator materials, in accordance with certain embodiments of thepresent disclosure. One or more vias 310 may be formed within thevertical stack, as illustrated in FIG. 3. The vias 310 have walls 312. Amasking layer (not shown) such as a photoresist, may be deposited overthe hardmask layer 208 in a pattern leaving exposed portions of thehardmask layer 208 where trenches are formed for patterning the hardmasklayer 208. Using an etch chemistry that will etch the material of thehardmask layer 208, those portions of the hardmask layer 208 exposed bythe patterned masking layer, i.e., photo-resist, disposed on top of thehardmask layer 208, may be removed. The hardmask layer 208 may be etchedwith the ionization of one or more process gasses, such as a chlorine(Cl) or fluorine (F) gas. In one example, the hardmask layer 208 mayhave two layers, a Cr layer disposed on the insulator layer 204 and aSiO₂ layer disposed on the Cr layer. F ions may be used to etch apattern in the SiO₂ layer exposing the Cr layer which the F ions willnot etch. The etchant may then be switched to Cl which will etch the Crwithout etching the SiO₂ in the hardmask layer 208 or the insulatorlayer 204 in the vertical stack 210 below the hardmask layer 208. Thehardmask layer 208 now has a pattern of openings exposing the verticalstack 210 for forming the vias 310A, 310B. The etchant may then beswitched back to F to etch the vias 310 into the vertical stack 210 downto the etch-stop layer 202. FIG. 3 illustrates two vias 310, via 310Aand via 310B. It should be appreciated that the number of vias 310formed in the vertical stack 210 may be significantly greater than therepresentative example to support a large storage capacity in the memorydevices. Furthermore, the etched vias may be in the form of a trench ortrenches.

At this stage, only portions of the vertical stack 210 where the vias310 are to be formed are exposed, and other portions are covered by thehard mask material. Thus, using an etch chemistry, such as F, that willetch the alternating layers of the insulator layers 204 and conductorlayers 206 in the vertical stack 210, vias 310, such as via 310A and310B, may be formed in the vertical stack 210 down to and exposing theetch-stop layer 202. The vias 310A, 310B may have substantially verticalwalls 312. The vertical walls 312 extend from the top surface 210 to theetch stop layer 202. In certain embodiments, a reactive-ion etching(RIE) process may be used to form vias 310A and 310B. Optionally, thehardmask layer 208 may be removed after the trenches are formed. Forexample, the remaining Cr layer in the hardmask layer 208 may be etchedaway with Cl, planarized or removed by another suitable method.

FIG. 4 illustrates a perspective view of the vertical stack 210 ofconductor layers 206 and insulator layers 204 comprising vias 310A,310B, 310C and 310D (collectively vias 310). In one embodiment, each via310 may be have a cylindrical shape extending through the vertical stackof conductor and insulator layers 204, 206 exposing the etch-stop layer202 (Not shown). In other embodiments, each of the vias 310 may have aprofile shape through the vertical stack 210 suitable for forming memorydevices therein. In one embodiment, each via 310 exposes a substantiallyflat surface portion of the etch-stop layer 202. The vias 310 may besubstantially equidistantly spaced apart such that a distance 328 fromadjacent vias is substantially similar throughout the vertical stack210. Alternately, the distance 328 between vias 310 may be arranged toaccommodate the packaging of the devices on a board or other interface.

FIG. 5 illustrates a plan view of the example vertical stack 210 in FIG.3 having material deposited for forming a memory cell, in accordancewith certain embodiments of the present disclosure. Each via 310 mayhave one or more addressable memory cells formed therein correspondingto the number of conductor layers 206 in the vertical stack 210. Thevias 310 may have a plurality of layers deposited therein forming one ormore memory cells adjacent each of the conductor layers 206 in thevertical stack 210. In one embodiment, four (4) layers of material aredeposited in the vias 310 along with a contact layer (conductive topelectrode 610 in FIG. 6) to form memory cells, e.g., memory cells 650,666, 670 illustrated in FIG. 6.

In one embodiment, a first layer 510 may be deposited on the verticalstack 210 and into the vias 310A, 310B forming on the walls 302 therein.The first layer 510 may be a memory layer suitable for forming memorycells such as those found in phase change (PCM) or resistive ram (RRAM)to name a few. Depending on the material used to plate the conductivelayers 206, the devices formed adjacent to the conductive layer 206 mayhave different electrical properties or may have properties affected bypassing a current therethrough. For example, in certain embodiments, amaterial may be used such that the device exhibits the electric propertyof a phase change material with a change in resistance. Such materialsmay be GeSbTe, SeTe, SiTe, SbSe, SnSe, SnTe, SnSb, GeSb, GeS, GeTe,SiSb, or alloys thereof. The device may also be a resistive RAM materialthat has different resistive states (e.g., HFO_(x), WO_(x), TaO_(x), ornT:O_(x)). An electrical behavior of phase change material ischaracterized by a shift from a blocking state (e.g., effectively anopen circuit or highly resistive state) to a resistive state, based onwhether a voltage applied to the phase change material reaches a certainthreshold. In other embodiments, a plating material may be used suchthat the device has a selector electric property of an ovonic thresholdswitch (OTS), such as GeSeBi. An OTS is a two terminal device thatshifts from a blocking state (e.g., a high resistive state) to aconductive state based on whether a voltage applied to the OTS reaches acertain threshold. Other selector materials can be alloys of GeSCu, orcopper (Cu) doped metal oxides such as Cu doped HFO₂. In one embodiment,the first layer 510 may be an oxide, such as a metal oxide. For example,the first layer 510 may be formed from aluminum monoxide (AlO), aluminumnitride (AlN), tantalum oxide (TaO_(x)), hafnium oxide (HfO_(x)), orother suitable material. The first layer 510 may be deposited orotherwise formed during a layer deposition process such as an atomiclayer deposition (ALD) process. The first layer 510 may have a thickness512 of between about 1nm to about 5 nm. In one embodiment, the thickness512 of the first layer 510 is about 2 nm.

A second layer 520 may be formed on the first layer 510. The secondlayer 520 may be a doped material. The electrical properties of thesecond layer 520 may be modified to effect the flow of electronstherethrough and thus the overall resistance of electrical pathwaythrough a device formed in the via 310. Alternately, the material of thesecond layer 520 may be selected from naturally occurring materials. Forexample, the second layer 520 may be formed from titania (TiO₂), zincoxide (Zn0), compounds thereof or other suitable materials. The secondlayer 520 may be deposited or otherwise formed during a layer depositionprocess such as an atomic layer deposition (ALD) process. The secondlayer 520 may have a thickness 522 of between about 10 nm to about 20nm, such as about 17 nm. In one embodiment, the second layer 520 isformed from TiO₂ by ALD to the thickness 522 of about 17 nm.

A third layer 530 may be formed on the second layer 520. The third layer530 may be a doped material. The third layer 530 may be formed fromaluminum oxide (Al₂O₃), aluminum monoxide (AlO), aluminum nitride (AlN),tantalum oxide (TaO_(x)), hafnium oxide (HfO_(x)) or other suitablematerial. The third layer 530 may be deposited or otherwise formedduring a layer deposition process such as an atomic layer deposition(ALD) process. The third layer 530 has a thickness 532 of between about1 nm and 5 nm, such as about 2 nm. In one embodiment, the third layer530 is formed from Al₂O₃ by ALD to the thickness 532 of about 2 nm.

A fourth layer 540 may be formed on the third layer 530. The fourthlayer 530 may be formed from titania (TiO₂), zinc oxide (Zn0), compoundsthereof or other suitable materials. The fourth layer 540 may bedeposited or otherwise formed during a layer deposition process such asan atomic layer deposition (ALD) process. The fourth layer 540 may havea thickness 542 of between about 1 nm and 5 nm, such as about 2 nm. Inone embodiment, the fourth layer 540 is formed from TiO₂ by ALD to thethickness 542 of about 2 nm.

In a second embodiment, the selector device 550 may be deposited on thevertical stack 210 and in the walls 312 of the vias 310A, 310B prior tothe deposition of the memory layer. For example, the selector device 550may include the first layer 510, the second layer 520, and the thirdlayer 530 and the memory layer may now be in the fourth layer 540. TiO₂having the thickness 512 of about 2 nm is deposited via an ALD processfor forming the first layer 510 on the wall 302 of the via 310. AlO_(x)having the thickness 522 of about 2 nm is deposited via an ALD processfor forming the second layer 520 on the first layer 510. TiO₂ having thethickness 512 of about 17 nm is deposited via an ALD process for formingthe third layer 530 on the second layer 520. The fourth layer 540 may bea memory layer formed on the third layer 530. The fourth layer 540 maybe formed from a metal oxide such as TiO_(x) or other suitable materialby an ALD process to the thickness 540 of about 2 nm. Thus, the order ofthe layers forming the selector device 550 and the memory cell may bereversed in the via 310.

Turning to FIG. 6, FIG. 6 illustrates a plan view of the examplevertical stack in FIG. 5 having memory cells 650, 660, 670 formedtherein, in accordance with certain embodiments of the presentdisclosure. The vertical stack 210 has a top surface 201. The verticalstack 210 may be etched to remove the first, second, third, and fourthlayers 510, 520, 530, 540 from the top surface 201 of the vertical stack210. Alternately, the top surface 201 may be planarized to remove thefirst, second, third, and fourth layers 510, 520, 530, 540.

A conductive top electrode 610 may be deposited on the vertical stack210. The conductive top electrode 610 may fill the vias 310. Theconductive top electrode 610 may form a continuous layer across the topsurface 201. The material of the conductive top electrode may bedeposited via chemical vapor deposition (CVD) or other suitable process.The conductive top electrode 610 may be formed from tungsten (W), copper(Cu), molybdenum (Mo), chromium (Cr), gold (Au), tantalum (Ta), apolycrystalline form of silicon, or other suitably electricallyconductive material. The conductive top electrode 610 for each via 310may be electrically isolated from adjacent vias 310. The conductive topelectrode 610 may be etched, trenched or electrically isolated by othersuitable methods.

The second, third and fourth layers 520, 530, 540 may form incombination a selector device 550 for the memory cells formed in thevias 310. For example, the selector device 550 may be formed from thethree layers 520, 530, 540 where the second layer 520 is made of TiO₂,the third layer 530 is Al₂O₃ and the fourth layer 540 is TiO₂. Theselector device 550 may have a total thickness 554 of less than 21 nm.The selector device 550 provides a conformal junction material to a 3-dmemory cell where the junction is adjacent to a non-volatile memorylayer (e.g. phase change or metal oxide layer), such as the first layer510. The selector device 550 and memory layer (i.e., first layer 510)allows for high density in the horizontal plane of the vertical stack aswell as vertically in multiple levels of the vias. The multiple levelsof interconnects in the selector device 550 minimizes sneak currentsbetween adjacent memory cells that complicate or confuse the readingdata stored in the memory cells. For example, a selector device 550,having the second layer 520 made of TiO₂, the third layer 530 of Al₂O₃and the fourth layer 540 of TiO₂, may demonstrate less than about 1 μAof sneak current when measuring 0.4 volts across the selector device550.

Optionally, a diffusion layer may be formed between the firsts layer 510and the wall 312 of the via 310. The diffusion layer may be depositedduring an ALD process prior to the deposition of the first layer 510.The diffusion layer may contain polysilicon, cobalt, tungsten, tantalum,or other suitable material. The diffusion layer may prevent the materialfrom the conductive layer 206 from transporting to the first layer 510.For example, the diffusion layer may act as a barrier and prevent goldin the conductive layer 206 from migrating into the TiO₂ of the firstlayer 510.

FIG. 7 illustrates a cross-sectional view through the conductive layer206 of the example vertical stack 210 of FIG. 6, in accordance withcertain embodiments of the present disclosure. The perspective view istaken through cross section line labeled 7-7. The cross section line 7-7horizontally slices the vertical stack at one of the conductor layers206 exposing memory cell 666. The memory cell 666 is a discrete locationalong the length of the memory layer addressed at the intersection ofthe conductor layer 206 and top electrode 610. The memory cell 666 isringed shaped. In one embodiment, the memory cell 666 may resides in thefirst layer 510. An outer perimeter 710 of the memory cell 666 is incontact with the conductor layer 206. An inner perimeter 712 of thememory cell is in contact with the selector device 550. Briefly viewingFIG. 6, it can be seen that the memory cell 666 may be addressed bysampling an electrical current through the pathway through theconductive top electrode 610A and conductive layer 664. The electricalcurrent may either store data or retrieve data from the memory cell 666.A value for the memory cell 666 may be measured by the currenttraversing the pathway. For example, the memory cell 666 may hold avalue of one (1) indicative of a first resistance or a value of zero (0)indicative of a second resistance. The total resistance along thepathway may be measured to determine the value, i.e., data, stored inthe memory cell 666.

In a second embodiment (not shown), a memory cell 680 may reside in thefourth layer 540. An inner perimeter 720 of the memory cell 680 is incontact with the conductive top electrode 610B. An outer perimeter 722of the memory cell 680 is in contact with the selector device 550.Briefly viewing FIG. 6, it can be seen that the memory cell 680 may beaddress by sampling an electrical current through the pathway throughthe conductive top electrode 610B and conductive layer 664. A value forthe memory cell 680 may be measured by the total resistance along thepathway similarly to the measuring of values stored in the memory cell666.

Thus, electrically addressing the memory cells 666, 680 formed in a 3-delement has been simplified. Each memory cells 666, 680 is electricallyisolating and addressing adjacent devices separated in the lateraldirection or vertical direction may be done with ease. The high densitymemory cells 666, 680 are substantially isolated electrically thusreducing or even eliminating sneak currents between the memory cells666, 680 making reading the memory easier and accurate. In oneembodiment, the memory cells are spaced 100 nm apart from adjacentmemory cells in the plane of the conductive layer 664. The memory cellsin the substrate may be individually addressed through the conductivelayers and the conductive top electrodes without sneak currentssubstantially altering the values determined by the electrical currentpassed therethrough.

The devices disclosed herein are scalable in 3D arrangements. It is tobe understood that the description herein is not limited to PCM and RRAMdevices, but rather is applicable to any memory cell, particularly thosememory cells requiring high density. The embodiments disclosed hereinare scalable, yet has a low footprint due to its 3D architecture.

While the foregoing is directed to embodiments of the presentdisclosure, other and further embodiments of the disclosure may bedevised without departing from the basic scope thereof, and the scopethereof is determined by the claims that follow.

What is claimed is:
 1. A method for fabricating a memory cell componentin a substrate, comprising: depositing an etch-stop layer on asubstrate; depositing in-plane alternating layers of conductor andinsulator materials over said etch-stop layer to create a vertical stackwherein the first and last layer is formed from the insulator material;depositing a hardmask layer on the vertical stack; etching a via havingwalls through the vertical stack to expose the etch-stop layer; removingthe hardmask; depositing a first layer on the wall of the via;depositing a second layer on the first layer; depositing a third layeron the second layer; depositing a fourth layer on the third layer;depositing a top conductor on the fourth layer; and forming one or morememory cells electrically connected to a portion of said top conductorand a portion of one of the in-plane layers of conductor material. 2.The method of claim 1, wherein the first layer is a memory materialformed from a metal oxide.
 3. The method of claim 2, wherein the metaloxide is one of AIN, TaO_(x), HfO_(x) or TiO_(x).
 4. The method of claim1, wherein the second, third and fourth layers form a selector devicehaving a thickness of about 21 nm.
 5. A method for fabricating a memorycell component in a substrate, comprising: depositing an etch-stop layeron a substrate; depositing in-plane alternating layers of conductor andinsulator materials over said etch-stop layer to create a vertical stackwherein the first and last layer is formed from the insulator material;depositing a hardmask layer on the vertical stack; etching a via havingwalls through the vertical stack to expose the etch-stop layer; removingthe hardmask; depositing a first layer on the wall of the via;depositing a second layer on the first layer; depositing a third layeron the second layer; depositing a fourth layer on the third layer;depositing a top conductor on the fourth layer; and forming one or morememory cells electrically connected to a portion of said top conductorand a portion of one of the in-plane layers of conductor material,wherein the second, third and fourth layers form a selector devicehaving a thickness of about 21 nm, and wherein the second layer is ofTiO₂ and has a thickness of about 17 nm, the third layer is of Al₂O₃ andhas a thickness of about 2 nm, and the fourth layer is of TiO₂ and has athickness of about 2 nm.
 6. The method of claim 1, wherein the fourthlayer is a memory material formed from a metal oxide.
 7. The method ofclaim 6, wherein the metal oxide is one of AIN, TaO_(x), HfO_(x) orTiO_(x) or alloys thereof.
 8. The method of claim 6, wherein the first,second, and third layers form a selector device having a thickness ofabout 21 nm.
 9. A method for fabricating a memory cell component in asubstrate, comprising: depositing an etch-stop layer on a substrate;depositing in-plane alternating layers of conductor and insulatormaterials over said etch-stop layer to create a vertical stack whereinthe first and last layer is formed from the insulator material;depositing a hardmask layer on the vertical stack; etching a via havingwalls through the vertical stack to expose the etch-stop layer; removingthe hardmask; depositing a first layer on the wall of the via;depositing a second layer on the first layer; depositing a third layeron the second layer; depositing a fourth layer on the third layer;depositing a top conductor on the fourth layer; and forming one or morememory cells electrically connected to a portion of said top conductorand a portion of one of the in-plane layers of conductor material,wherein the fourth layer is a memory material formed from a metal oxide,wherein the first, second, and third layers form a selector devicehaving a thickness of about 21 nm, and wherein the third layer is ofTiO₂ and has a thickness of about 17 nm, the second layer is of AIN andhas a thickness of about 2 nm, and the first layer is of TiO₂ and has athickness of about 2 nm.